Required Skills: LPDDR5X, PCIe Gen7, and UCIe (64G)
Job Description
Job Title: Signal Integrity (SI) & Power Integrity (PI) Engineer
Experience: 5+ Years
Location: San Jose (Work from Office / Onsite)
We’re looking for an experienced Packaging Designer to develop creative and cost-effective IC package designs.
Role Overview:
We are seeking a Signal Integrity Engineer to support high-speed interface development and validation. You’ll work on cutting-edge technologies such as LPDDR5X, PCIe Gen7, and UCIe (64G), collaborating closely with design, package, and PCB teams to ensure top performance.
Responsibilities:
- Perform channel modeling, extractions, and eye analysis for high-speed interfaces.
- Conduct pre- and post-layout simulations to ensure standard compliance.
- Analyze crosstalk, reflections, jitter, insertion/return loss.
- Execute power integrity extractions and simulations for high-speed interfaces.
- Model and analyze package/board PDN, define decoupling strategy, and validate performance.
- Collaborate across teams to optimize SI/PI performance.
- Generate technical reports and recommendations for design decisions.
- Provide SI/PI design guidelines aligned with system requirements.
Qualifications: